60% of All Transistors are Made Up on the Spot

CNet News wonders why, Despite its aging design, the x86 is still in charge.

The article includes this quote from Simon Crosby, CTO of XenSource:

There’s no reason whatsoever why the Intel architecture remains so complex. There’s no reason why they couldn’t ditch 60 percent of the transistors on the chip, most of which are for legacy modes.

Wow. 60%? What a huge waste! Could that really be true? Lets take a look at a random K8 die shot from the inter-web:

K8 die shot

Hmm. See that highly regular pattern that comprises the right half the chip? That would be cache.

Lets assume that Crosby meant 60% of the other part. You know, the not-cache stuff. Even if we are most charitable, he still wrong. We could perhaps simplify the front end of the chip (marked above as “Fetch Scan Align Micro-code.”) Still, much of that section is for the branch predictor and TLB, which might be good to keep around.

If I were going to invent a number, I’d have picked something much closer to 1%.


5 Responses to “60% of All Transistors are Made Up on the Spot”

  1. 1 Kevin April 4, 2007 at 12:53 pm

    80% of all virtual server installations are worthless…

  2. 2 Nathan Zook June 11, 2007 at 5:41 pm

    It’s not just scan/align. Memory segmentation/subsegmentation / I/O / PIC are all hopelessly out-of-date and needlessly complicated. A clean 64-bit design would probably run 5-10% faster with 5-10% fewer non-cache functional transistors.

    So 55% of transistors are made up on the spot.

  3. 3 Mark June 11, 2007 at 8:18 pm

    Thanks for the comment, Nathan.

    When I originally wrote this, I was thinking more along the lines of “if we spoke some RISC ISA instead of x86”, although, admittedly, this is not what Crosby said. It makes sense that removing the “legacy modes” would improve things other than the front end, for example (as you note) something like the load store unit.

    I guess I’m willing to believe your “5-10% fewer non-cache” transistors, but I still have a somewhat hard time accepting the clock advantages. Are there really speed paths through this legacy stuff?

    Going back to the LSU as an example, K8 still supports the segmented addressing scheme, but you pay another cycle whenever you use it. Seems less like “overhead” and more like “pay as you go”.

    Away, thanks again for the comment. Good to see another AMDer somewhere besides comp.arch 🙂

  4. 4 Nathan Zook June 14, 2007 at 4:17 pm

    It’s REALLY good to be back (at AMD)…

    A clean design is about more than just pulling speed paths out of legacy modes. I’m talking about potentially needing to access memory 15 separate times in order to execute a single load/store instruction I’m talking about wasting a cycle to find out where you are in a register file. (Yes, flat mode is available now for the FPU, but this is the sort of thing that never even comes up in a clean design.)

    One of the useful things at working at an evil company for a while was that I got to learn about a totally different architecture. Not that it was still clean, but it opened up the possibilities.

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