The Case for RISC

I’ve been reading Patterson’s classic RISC manifesto tonight.

I find nearly all of his arguments compelling. I’m so credulous. I’ve got to disagree with something or I’ll lose my CISC-zealot card. Ah, here we are:

Better use of chip area.
If you have the area, why not implement the CISC? For a given chip area there are many tradeoffs for what can be realized. We feel that the area gained back by designing a RISC architecture rather than a CISC architecture can be used to make the RISC even more attractive than the CISC. For example, we feel that the entire system performance might improve more if silicon area were instead used for on-chip caches [Patterson,Srquin80], larger and faster transistors, or even pipelining. As VLSI technology improves, the RISC architecture can always stay one step ahead of the comparable CISC. When the CISC becomes realizable on a single chip, the RISC will have the silicon area to use pipelining techniques; when the CISC gets pipelining the RISC will have on chip caches, etc. The CISC also suffers by the fact that its intrinsic complexity often makes advanced techniques even harder to implement.

I think this one ended up not being a very big deal. Once we started translating the software-visible CISC ops into internal micro-ops, we got most of the advantages of RISC. The decoder is a complex machine, but we solved it once and now it’s just a fixed amount of overhead.

But what the heck do I know — I’m a software guy. I’m just parroting the hardware gurus.


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